(1) Field of the Invention
The invention relates to the field of manufacturing of semiconductor wafers. More specifically, the invention relates to the formation of metal lines and vias as part of interconnect systems on semiconductor wafers.
(2) Background Information
Modern integrated circuits typically contain multiple layers of metal lines and vias which electrically connect the millions of passive and active devices such as transistors, capacitors and resistors in the integrated circuits. The multiple layers of metal lines and vias are collectively known as xe2x80x9cinterconnectsxe2x80x9d or the metallization of the integrated circuit. The characteristics and quality of the interconnects or metallization is a key component affecting the performance and reliability of the integrated circuit.
In contemporary semiconductor processing, aluminum metallization is most commonly used because aluminum is inexpensive and the manufacturing processes required to form aluminum metallization are relatively simple. However, as semiconductor device sizes are reduced below 0.25 um and the clock speeds increase above 500 MHz, aluminum is rapidly becoming undesirable as an interconnect material because of its relatively poor electromigration and conductivity properties. It has become highly desirable to fabricate interconnects from noble metals such as copper because noble metals are more conductive and more immune to electromigration.
One method of fabricating noble metal interconnects is known as the xe2x80x9cDamascenexe2x80x9d process. According to this process, a dielectric layer such as silicon oxide, which is deposited on the substrate, is etched to form via holes and oxide trenches. A noble metal such as copper is then deposited into the oxide trenches, via holes, and field areas by way of sputtering and electroplating. The unwanted noble metal in the field areas is then removed using chemical-mechanical polishing (CMP) methods. Unfortunately, certain aspects of the Damascene process are difficult to control, especially the CMP of the noble metal.
An alternate noble metal interconnect fabrication process has been developed to overcome some of the problems associated with the Damascene process. This process is documented in the patent application xe2x80x9cA Single Step Electroplating Process for Interconnect Via Fill and Metal Line Patterning,xe2x80x9d Ser. No. 09/001,349 assigned to Intel Corporation of Santa Clara, Calif. Briefly, this process consists of introducing a barrier layer onto the surface of a substrate which has via holes. Over the barrier layer, a conductive layer is introduced followed by a photoresist layer. Noble metal via plugs and noble metal lines are then formed simultaneously using an electroplating process. The layer of photoresist is then removed, and the conductive layer and barrier layer are etched in areas where they are not covered by metal lines.
Perhaps the most challenging aspect in the above-referenced process is the requirement to etch the conductive layer, typically made of nickel, while leaving the noble metal lines, typically made of copper, and the barrier layer, typically made of titanium nitride, substantially unaffected. One method of etching the conductive layer while leaving the copper lines unaffected is to use a wet etchant. Many wet etchant formulations designed for etching nickel from copper substrates are documented in the literature and some are commercially available. However, these wet etchant formulations typically contain additives such as thiourea, ammonium thiocyanate, or sodium diethyldithiourea to inhibit the etchant from attacking the exposed copper. Unfortunately, these additives tend to cause formation of a dark residue (i.e., black smut) on the exposed copper interconnect surfaces, and this dark residue is difficult to remove after the etching process is complete. In addition, the rate at which the wet etchant removes the nickel layer tends to decrease quickly with use. Consequently, the etching process can be difficult to control. Accordingly, a need exists for an improved process of selectively etching the conductive film with minimal attack of the exposed noble metal interconnects and vias.
The invention provides in one embodiment thereof, a process to selectively remove a conductive film from a substrate. According to this process, a substrate having sub-micron interconnect features is placed in an electrolyte solution. The substrate is coupled to a working electrode terminal of a potentiostat. A voltage is maintained between the substrate and a reference electrode at a fixed value by varying a current between the substrate and a counter electrode. A path of the current is broken when the current has a second current value substantially lower than a first current value.